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PD-97111
IP1202PBF
Dual Output Full Function 2 Phase Synchronous Buck Power Block
Features
* * * * * * * * * * * * * * * * 5.5V to 13.2V input voltage 0.8V to 5V output voltage 2 Phase Synchronous Buck Power Block 180 out of phase operation Single or Dual output capability Dual 15A maximum load capability Single 2 phase 30A maximum load capability 200-400kHz per channel nominal switching frequency Over Current Hiccup or Over Current Latch External Synchronization Capable Overvoltage protection Individual soft start per outputs Over Temperature protection Internal features minimize layout sensitivity * Ease of layout Very small outline 15.5mm x 9.25mm x 2.6mm
Integrated Power Semiconductors, PWM Control & Passives
IP1202PBF Power Block
Description The IP1202PBF is a fully optimized solution for medium current synchronous buck applications requiring up to 15A or 30A. The IP1202PBF is optimized for 2 phase single output applications up to 30A or dual output, each up to 15A with interleaved input. It includes full function PWM control, with optimized power semiconductor chipsets and associated passives, achieving high power density. Very few external components are required to create a complete synchronous buck power supply. iPOWIR technology offers designers an innovative space-saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection. IP1202PBF Configurations
Channel 1
V IN
V OUT
V IN
V OUT
Channel 2
V OUT
Single Output
Dual Output
* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be applied for the design of the power supply board. The iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable and reliable long term operation. See layout guidelines in datasheet for more detailed information.
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8/16/06
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IP1202PBF
Parameter VIN Feedback Output Overvoltage Sense PGOOD ENABLE Soft Start Vp-ref HICCUP SYNC Output RMS Current Per Channel Block Temperature
All specifications @ 25C (unless otherwise specified)
Symbol VIN VFB1/VFB2 VFB1S/VFB2S Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 Typ Max 15 6 6 15 15 6 6 15 6 15 125 Units Conditions
Absolute Maximum Ratings
V
SS1/SS2 HICCUP IoutVSW TBLK
A C
2 Independent outputs. See Fig. 3 Capable of start up over full temperature range. See Note 1.
Recommended Operating Conditions
Parameter Input Voltage Range Output RMS Current Per Channel Symbol VIN IoutVSW Output Voltage Range VOUT 0.8 0.8 11 5.0 3.3 A V Min 5.5 Typ Max 13.2 15 Units A Conditions
2 Independent outputs TPCB = TCASE = 90C. See Fig. 3 2 Independent outputs TPCB = 90C, TCASE = no airflow, no heatsink. See Fig. 3 For VIN = 12V For VIN = 5.5V
Electrical Specifications @ VIN = 12V
Parameter Power Loss Over Current Shutdown HICCUP duty cycle Soft Start Time Reference Voltage VOUT Accuracy Symbol PLOSS IOC DHICCUP tSS VREF VOUT_ACC1 VOUT_ACC2 VOS2 IBFB IERR gm1, gm2 OVP tOVP VTh_PGOOD VLO_PGOOD -3 -2.5 -4 Min Typ 7.0 25 5 5 0.8 -0.1 60 2000 1.15 x VOUT 25 0.85 x VOUT 0.25 3 2.5 4 mV A A mho V s V V
See OVP note in Design Guidelines Output forced to 1.125Vref FB1 or FB2 ramping down ISINK=2mA
Max 8.75 -
Units W A % ms V %
Conditions
fSW = 300kHz, VIN = 12V, TBLK= 25C VOUT1 = VOUT2 = 1.5V, IOUT1 = IOUT2= 15A VIN = 12V, VOUT = 1.5V fSW = 300KHz, ROCSET = 51.1k HICCUP pin pulled Low HICCUP pin pulled high, output short circuited. VIN = 12V, VOUT = 1.5V, CSS1= CSS2=0.1F TBLK = -40C to 125C, See Note 1. VIN= 12V, VOUT = 1.5V TBLK = 0C to 125C, See Note 1. VIN= 12V, VOUT = 1.5V VIN = 12V, VOUT = 1.5V, specified for current share accuracy in parallel configuration. Rshunt1 = Rshunt2 =5m , Iout= 30A. See Fig. 15
Error Amplifier 2 input offset voltage FB1/FB2 Input bias current Error Amplifier source/sink Current Error Amplifier Transconductance Output Overvoltage Shutdown Threshold OVP Fault Propagation Delay PGOOD Trip Threshold PGOOD Output Low Voltage
2
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IP1202PBF
Electrical Specifications (continued)
Parameter Frequency Oscillator Ramp Voltage SYNC Frequency Range SYNC Pulse Duration SYNC, HICCUP High Level Threshold Voltage SYNC, HICCUP Low Level Threshold Voltage VIN Quiescent Current Thermal Shutdown Max Duty Cycle ENABLE Threshold Voltage VIN Turn On Threshold Voltage VIN Turn Off Threshold Voltage Output Disable Voltage Soft Start Low Threshold Voltage Symbol fSW Vramp fSYNC tSYNC Min 170 255 340 480 2 IIN-LEAKAGE Tempshdn DMAX VEN-LO VON_th VOFF_th VSS-DIS 85 5 Typ 1.25 200 15 140 4.8 4.3 Max 230 345 460 800 0.8 0.25 Units kHz kHz kHz V kHz ns V V mA C % V V V V
fSW= 200kHz, TBLK = 25C Measured between VIN and ENABLE Measured at start of soft start, ENABLE pulled low, VIN ramping up Measured at fall of soft start, ENABLE pulled low, VIN ramping down SS1 / SS2 Pins Pulled Low VIN = 12V, ENABLE high
Conditions
RT = 48.7k RT = 30.9k RT = 21.5k Free running frequency set 20% below sync frequency ( See Fig.9 for RT selection )
Note 1: Guaranteed to meet specifications from TBLK = 0C to 90C. Specifications outside of this temperature range are guaranteed by design, and not production tested.
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IP1202PBF
4
VCC VIN ENABLE HICCUP 25uA
Bias Generator
SS1 3uA
UVLO
SW1
64uA 25uA 3uA Error Amp1
R Q
OC Latch / Hiccup Control Driver 1
VSW1 SW2 20k
SS2 PWM Comp1
0.8V PWM1
S
25k
64uA
OCSET1
FB1
25k
CC1 Ramp1
Two phase Oscillator
PGND SW3
SYNC
RT PWM Comp2
Driver 2
VREF Error Amp2 Ramp2
0.8V
VSW2 SW4 PWM2 20k
Fig. 1: IP1202PBF Internal Block Diagram
S Q R
VP-REF
25k
FB2
25k
CC2
PGood (-10%) OVP (+15%)
OCSET2 PGOOD
FB1S
FB2S
SW1 / SW3 OFF SW2 / SW4 ON
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IP1202PBF
12 11 V IN = 12V V OUT 1 = V OUT 2 = 1.5V f SW = 300kHz L = 1.0H TBLK = 125C
M aximum
Total Power Loss, Both Outputs (W)
10 9 8 7 6 5 4 3 2 1 0 0 1
T ypical
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Output Current per Channel (A)
Fig. 2: Power Loss vs. Current
Case Temperature (&
16 15 14 13 0 10 20 30 40 50 60 70 80 90 100 110 120
Output Current Per Channel (A)
12 11 10 9 8 7 6 5 4 3 2 1 0 0 10 20
Safe Operating Area
TX V IN = 12V V OUT 1 = V OUT 2 = 1.5V IOUT = 15A f SW = 300kHz L = 1.0 H 30 40 50 60 70 80 90 100 110 120
PCB Temperature (C)
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Fig. 3: Safe Operating Area (SOA) vs. TPCB & TCASE
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IP1202PBF
1.060 1.045 VOU T 1 =VOU T 2 =1.5V I OU T 1 =I OU T 2 =15A f S W =300kHz L =1.0 H T B L K =125C 2.0 1.5 1.0 0.5 0.0 - 0.5 - 1.0 - 1.5 - 2.0 - 2.5 5 6 7 8 9 10 11 12 13 14
1.120 1.105 VI N =12V I OU T 1 =I OU T 2 =15A f S W =300k Hz L =1.0 H T B L K =125C 4.0 3.5
SO A Temp Adjustment ( 0 C)
SOA Temp Adjustment (C)
Norm alized Power Loss
1.030 1.015 1.000 0.985 0.970 0.955 0.940 0.925
Normalized Power Loss
1.090 1.075 1.060 1.045 1.030 1.015 1.000 0.985 0.970 0.955 0.5 1
3.0 2.5 2.0 1.5 1.0 0.5 0.0 - 0.5 - 1.0 - 1.5
1.5
2
2.5
3
3.5
4
4.5
5
Input Voltage (V)
Output V oltage (V )
Fig. 4: Normalized Power Loss vs. VIN
1.060 1.045 VI N =12V VOU T 1 =VOU T 2 =1.5V I OU T 1 =I OU T 2 =15A L =1.0 H T B L K =125C 2.0 1.5 1.0 0.5 0.0 - 0.5 - 1.0 - 1.5 - 2.0 - 2.5 - 3.0 250 300 350 400
1.24 1.21
Fig. 5: Normalized Power Loss vs. VOUT
8.0 VI N =12V VOU T 1 =VOU T 2 =1.5V I OU T 1 =I OU T 2 =15A f S W =300kHz 1.15 1.12 1.09 1.06 1.03 1.00 0.97 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 T B L K =125C 5.0 4.0 3.0 2.0 1.0 0.0 - 1.0 7.0 6.0
SOA Temp Adjustment ( C)
SOA Temp Adjustment (C)
Normalized Power Loss
Normalized Power Loss
1.030 1.015 1.000 0.985 0.970 0.955 0.940 0.925 0.910 200
1.18
Sw itching Fre que ncy (k Hz)
Output Inductance ( P H)
Fig. 6: Normalized Power Loss vs. Frequency
55 205 185 165 145 125
V in = 12V
Fig. 7: Normalized Power Loss vs. Inductance
400
ROC-SET (kOhms) for 12Vin
50 45 40 35 30 25 20 15 10 5
6
Switching Frequency in kHz
V OUT = 1.5V f = 300kHz sw L = 1.0H T BLK = 125C
ROC-SET (kOhms) for 5.5Vin
380 360 340 320 300 280 260 240 220 200 20 25 30 35 40 45 50
105 85
V in = 5.5V
65 45 25 5
8
10
12
14
16
18
20
22
24
Overload Current (A)
R T in kOhms
6
Fig. 8: Nominal Overcurrent Threshold Setting External Resistor Selection
Fig. 9: Per Channel Switching Frequency vs RT www.irf.com
IP1202PBF
Applying the Safe Operating Area (SOA) Curve
The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn Cas e Te m pe ratur e (8A out through the printed circuit board and the top of the case.
Procedure
1) Draw a line from Case Temp axis at TCASE to the PCB Temp axis at TPCB. 2) Draw a vertical line from the TX axis intercept to the SOA curve. (see AN-1047 for further explanation of TX ) 3) Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y axis. The point at which the horizontal line meets the y-axis is the SOA current. 4) If no top sided heatsinking is available, assume TCASE temperature of 125C for worst case performance.
Output Current (A)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
10
20
30
40
50
60
70
80
90
100
110
120
3 1
Safe Operating Area
2
TX
V IN = 12V V OUT 1 = V OUT 2 = 1.5V IOUT = 15A f S W = 300kHz L = 1.8uH 0 10 20 30 40 50 60 70 80 90 100 110 120
PCB Temperature (C)
Adjusting the Power Loss and SOA curves for different operating conditions
To make adjustments to the power loss curves in Fig. 2, multiply the normalized value obtained from the curves in Figs. 4, 5, 6 or 7 by the value indicated on the power loss curve in Fig. 2. Remember that the power loss in Fig 2. is the power loss for 2 outputs operating with the same output voltage. If differing output voltages are used the initial power loss for each channel needs to be divided by 2. Then if multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 2. The resulting product is the final power loss based on all factors. See example no. 1. To make adjustments to the SOA curve in Fig. 3, determine your maximum PCB Temp & Case Temp at the maximum operating current of each IP1202PBF. Then, add the correction temperature from the normalized curves in Figs. 4, 5, 6 or 7 to the TX axis intercept (see procedure no. 2 above) in Fig. 3. When multiple adjustments are required, add all of the temperatures together, then add the sum to the TX axis intercept in Fig. 3. See example no. 2. Operating Conditions for the following examples: Output1 Output Current = 12A Output Voltage = 1.2V Output Current = 10A Output Voltage = 3.3V Input Voltage = 8V Sw Freq= 300kHz Input Voltage =8V Sw Freq= 300kHz Inductor = 1.75H
Output2
Inductor = 1.75H
Example 1) Adjusting for Maximum Power Loss: Output1 (Fig. 2) Maximum power loss = W 8.25/2 = 4.125W (Fig. 4) Normalized power loss for input voltage 0.93 (Fig. 5) Normalized power loss for output voltage 0.98 (Fig. 6) Normalized power loss for frequency 1.0 (Fig. 7) Normalized power loss for inductor value 0.98 Adjusted Power Loss = 4.125 x 0.93 x 0.98 x 1.0 x 0.98 3.7W
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IP1202PBF
Output2 (Fig. (Fig. (Fig. (Fig. (Fig. 2) 4) 5) 6) 7) Maximum power loss =6.4W /2 = 3.2W Normalized power loss for input voltage 0.93 Normalized power loss for output voltage 1.075 Normalized power loss for frequency 1.0 Normalized power loss for inductor value 0.98 Adjusted Power Loss = 3.2W x 0.93 x 1.075 x 1.0 x 0.98 3.13W Total device power loss = 3.7W + 3.13W 6.8W Example 2) Adjusting for SOA Temperature: Assuming TCASE = 110C & TPCB = 90C for both outputs Output1 (Fig. 4) Normalized SOA Temperature for input voltage -2.3C (Fig. 5) Normalized SOA Temperature for output voltage -0.6C (Fig. 6) Normalized SOA Temperature for frequency 0C (Fig. 7) Normalized SOA Temperature for inductor value -0.7C TX axis intercept temp adjustment = -2.3C - 0.6C + 1.9C - 0.7C -3.6C The following example shows how the SOA current is adjusted for a TX change of -3.6C and output 1 is in SOA
Cas e Te m pe rature (8A 50 60 70 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 110 120 V IN = 12V V OUT 1 = V OUT 2 = 1.5V IOUT = 15A f SW = 300kHz L = 1.8uH A djusted SOA Current Unadjusted SOA Current 0 10 20 30 40 80 90 100 110 120
Output Current (A)
Safe Operating Area
TX
PCB Temperature (C)
Output2 (Fig. 4) (Fig. 5) (Fig. 6) (Fig. 7)
Normalized SOA Temperature for input voltage -2.3C Normalized SOA Temperature for output voltage 3.9C Normalized SOA Temperature for frequency 0C Normalized SOA Temperature for inductor value -0.7C
TX axis intercept temp adjustment = -2.3C + 3.9C - 0C - 0.7C 0.9C The following example shows how the SOA current is adjusted for a TX change of 0.9C and output 2 is in SOA.
Cas e Te m pe ratur e (8A 16 15 14 13 12 A djusted SOA Current 11 10 9 8 7 6 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 110 120 V IN = 12V V OUT 1 = V OUT 2 = 1.5V IOUT = 15A f SW = 300kHz L = 1.8uH Unadjusted SOA Current 0 10 20 30 40 50 60 70 80 90 100 110 120
Output Current (A)
Safe Operating Area
TX
8
PCB Temperature (C)
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IP1202PBF
Pin Name VIN CC1 CC2 ENABLE SS1 SS2 FB1 FB1s FB2 FB2s VSW1 VSW2 Ball Designator A1 A2 A3 A4 A15 A16 A17 A18 B1 B2 B3 B4 B15 B16 B17 B18 C1 C2 C3 C4 C15 C16 C17 C18 H6 H13 A8 B8 H8 H11 J6 J8 J13 J11 D1 D2 D3 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 K1 K2 L1 L2 D16 D17 D18 E17 E18 F17 F18 G17 G18 H17 H18 J17 J18 K17 K18 L17 L18 A5 A6 A7 A9 A10 A12 A13 A14 B5 B6 B7 B10 B11 B12 B13 B14 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E3 E4 E5 E6 E13 E14 E15 E16 F3 F4 F5 F6 F8 F9 F10 F11 F13 F14 F15 F16 G3 G4 G6 G9 G10 G13 G15 G16 H4 H9 H10 H15 J4 J5 J9 J10 J14 J15 K4 K5 K14 K15 L3 L4 L5 L13 L14 L15 L16 L9 Pin Description Input voltage connection pins Output of the first error amplifier Output of the second error amplifier Single pin for both outputs. Commands ouputs ON or OFF. Normally Pulled High. Pulled low, turns both outputs ON. Soft start pin for output 1. External capacitor provides soft start. Pulling soft start pin low will disable this output. Soft start pin for output 2. External capacitor provides soft start. Pulling soft start pin low will disable this output. Inverting input of error amplifier 1 Output 1 overvoltage sense pin. Inverting input of error amplifier 2 Output 2 overvoltage sense pin. Output 1 inductor connection pins Output 2 inductor connection pins
PGND
Power Ground pins
Vref
Amplifier 1 reference Voltage. Connect a 100pF cap from this pin to PGND. Amplifier 2 reference voltage. Connect to Vref for independent output configuration. Refer to application notes on how to connect to parallel configuration or output voltage tracking configurations. External Clock synchronization pin. Set free running frequency to 80% of the SYNC frequency. When not in use, leave pin floating Switching frequency setting pin. For RT selection, refer to Fig.9 of the datasheet. Power Good pin. Open collector, requires external pulll-up. If function not needed, pin can be left floating Logic level pin. Pulled high enables hiccup mode of operation. Pulled low enables latched overcurrent shutdown mode. Overcurrent trip threshold pin for output 1 Overcurrent trip threshold pin for output 2
VP-ref
L8
SYNC RT PGOOD HICCUP OCSET1 OCSET2
K6 L11 L10 L6 G8 G11
Table 1: Pin Description
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IP1202PBF
Iin Average
A
V
Vin Average
Cin
Vin DC
PIN = VIN Average x IIN Average POUT = (VOUT1 Average x IOUT1 Average) + + (VOUT2 Average x IOUT2 Average) PLOSS = PIN - POUT
Vout1 Iout1
Iout1 Average
VSW1
Lo1 Co1
VIN
A
FB1
IP1202PBF iP1202
FB2
Averaging Circuit 1
V
Vout1 Average Iout2 Average
A
Lo2
PGND VSW2
Vout2 Iout2
Co2
Averaging Circuit 2
V
Vout2 Average
Fig. 10: Power Loss Test Circuit
10
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IP1202PBF
ENABLE
VIN
VIN
PGND OCSET1 CC1 SS1 FB1 FB1s SYNC Vref PGOOD RT OCSET2 CC2 SS2 FB2 FB2s
PGND
VSW1
VSW2
HICCUP VP-ref
All Dimensions in inches (millimeters) Fig. 11: Recommended PCB Footprint (Top View) www.irf.com 11
IP1202PBF
IP1202PBF Users Design Guidelines
The IP1202PBF can be configured as a dual channel 15A or parallel single 30A power block consisting of optimized power semiconductors, PWM control and its associated passive components. It is based on a synchronous buck topology and offers an optimized solution where space, efficiency and noise caused by parasitics are of concern. The phase shifted, two output power block operates with fixed frequency voltage mode control and can be configured to operate as a dual output or paralleled single output with current sharing. The IP1202PBF components are integrated in a ball grid array (BGA) package. VIN The input operating voltage range of the IP1202PBF is 5.5V to 13.2V. Both channels of the power block have a common input. Enabling the Outputs The ENABLE pin turns on and turns off both outputs of the IP1202PBF simultaneously. The IP1202PBF outputs will be turned off by floating the ENABLE pin. ENABLE low will start the outputs. The converter can also be shutdown by pulling the soft-start pins to PGND through a logic level MOSFET the drain of which connects to the soft start pin (see Fig.12). This feature can be useful if sequencing or different startup timing of the outputs are required. In situations where the output has undergone a latched shutdown due to overvoltage or overcurrent, cycling ENABLE will reset the outputs. Cycling soft start pins will not unlatch the outputs. Dual Soft Start The Soft Start function provides a controlled rise of the output voltage, thus limiting the inrush current during start-up. The IP1202PBF provides two independent soft start functions. The soft start pins can be connected to the soft start capacitors to provide different start-up and sequencing profiles. Each soft start function has an internal 25uA +/-20% current source that charges the external soft start capacitor Css up to 3V. During power-up, the output voltage starts ramping up only after the charging voltage across the C ss capacitor has reached a 0.8Vtyp threshold, as shown in Fig. 13. 12 Fig. 12: Soft Start/Enable Circuit
3V
This threshold voltage should be taken into consideration when designing sequencing profiles using the IP1202PBF as it will effect start-up delays and ramp-times. For proper implementation of sequencing of outputs using the IP1202PBF, refer to IR Application Note AN-1053 - Power sequencing techniques using iP1201 and IP1202PBF.
Iss SS1/SS2 iP1202 IP1202PBF
Css
0.8Vtyp VCss VOUT
Fig. 13: Power Up Threshold Mode of Operation The IP1202PBF can be configured to provide either two independent dual outputs or single paralleled output with current share. In dual output mode, the two error amplifiers of the PWM controller operate independently. Each output voltage of the IP1202PBF block is controlled by its own error amplifier. The output of the error amplifier and the internally generated ramp signal are compared to produce PWM pulses of fixed frequency that drive the internal power switches. In this mode, the VP-ref pin must be connected to Vref pin. Vref pin is the internally generated 0.8V reference input of first error amplifier . Refer to the internal block diagram of the IP1202PBF in Fig.1. In single output mode, one error amplifier controls the output voltage and the other amplifier monitors www.irf.com
IP1202PBF
the inductor current information for current sharing. In this mode, VP-ref pin must be disconnected from Vref pin and connected to the output of channel1 inductor, see Fig. 15. The inductor current information is provided through external shunts placed in series with the output inductors. A lossless inductor current sensing scheme can also be implemented as shown in Fig.16, where the current is sensed through the DC resistance of the inductor. In this case RL and CL are selected such that RLx CL = L / Rdc. Set RL = 1K and solve for CL. Rdc is the internal DC resistance of inductor L. In single output two phase mode, leave SS2 pin open. The IP1202PBF can also be configured in dual output tracking mode where the second output tracks the first output. For a specific output configuration, follow the connection diagram shown in Fig.14, Fig.15, Fig.16 at the end of this section. Out of Phase Operation The dual output PWM controller inside the IP1202PBF provides a 180 out of phase operation of the PWM outputs. This method of control offers the advantage of reducing the amount of input bypass capacitors due to increase in input ripple frequency and hence reduction of ripple amplitude. Moreover, for paralleled output configurations 180 phase shifting contributes to smaller output capacitors due to output inductor ripple current cancellation and ripple reduction. Frequency and Synchronization The operating switching frequency (fSW) range of IP1202PBF is 200 kHz to 400 kHz. The desired frequency is set by placing an external resistor to the RT pin of the IP1202PBF. See Fig. 9 for the proper resistor value. The IP1202PBF is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge clock. The free running oscillator frequency is twice the per-channel frequency. During synchronization, RT is selected such that the free running frequency is 20% below the synchronization frequency. The maximum synchronization frequency that IP1202PBF can accept is 800kHz. Note that the actual free running frequency of individual output is half the synchronization frequency. www.irf.com Synchronization capability is provided both in independent and parallel configurations. When unused, the SYNC pin must be left floating. Overcurrent Protection/Autorestart The Overcurrent Protection function of the IP1202PBF offers two distinct modes: HICCUP of the output and Overcurrent Shutdown. If the Hiccup pin is pulled high (Hiccup enabled), hiccup mode will be selected. If Hiccup pin is pulled low (Hiccup disabled), overcurrent shutdown will be selected. During overloads, in HICCUP disabled mode, the controller shuts down as soon as the trip threshold is reached. In HICCUP enabled mode, when overcurrent trip threshold is reached, the power supply output shuts down and attempts to restart. The time duration between the shutdown of the output and the restart is determined by the time it takes to discharge the soft start capacitor. Typically, the discharge time of the soft start capacitor is 10 times the charge time. The duty cycle of the hiccup process is typically 5%. The output will stay in hiccup indefinitely until the overload is removed. The typical overcurrent trip threshold of the device is internally set at 30A. The overcurrent shutdown / HICCUP threshold is 30% accurate. The IP1202PBF overcurrent shutdown and HICCUP threshold can be set externally by adding ROCSET1 and ROCSET2 resistors from OCSET1 and OCSET2 pins to VSW1 and VSW2 pins respectively. Refer to Fig.8 for ROCSET1 and ROCSET2 selection. Overvoltage Protection (OVP) Overvoltage is sensed through separate output voltage sense pins FB1s and FB2s. A separate OVP circuit is provided for each output and the OVP threshold is set to 115% of the output voltage. Upon overvoltage condition of either one of the outputs, the OVP forces a latched shutdown on both outputs. In this mode, the upper FETs turn off and the lower FETs turn on, thus crowbaring the outputs. Reset is performed by recycling the ENABLE pin. Overvoltage can be sensed by either connecting FB1s and FB2s to their corresponding outputs through separate output voltage divider resistor networks, or they can be connected directly to their corrsponding feedback pins FB1 and FB2. For Type III control loop compensation, FB1s and FB2s should be connected through voltage dividers only. 13
IP1202PBF
Refer to IP1202PBF Design Procedure section on how to set the OVP Trip threshold. PGOOD This is an output voltage status signal that is open collector and is pulled low when the output voltage falls below 85% of the output voltage. High state indicates that outputs are in regulation. There is only one PGOOD for both outputs. The PGOOD pin can be left floating if not used. Thermal Shutdown The IP1202PBF provides thermal shutdown. The threshold typically is set to 140C. When the trip threshold is exceeded, thermal shutdown turns the outputs off. Thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to the normal range.
VIN 12V
Cin 22uF x6 R1 100k
VIN
OC1 VSW1 FB1
ROC1 51.1k L1 1.0uH R9 887
VOUT1 1.5V Cout1 470uF x2
HICCUP
FB1S
C9
CC1
R7 1k
0.018uF R2 100k C8 0.1uF
PGOOD SS1
R5 2.49k
IP1202PBF
SS2
iP1202
VP-REF VREF
0.8V C10 100pF
C7 0.1uF
OC2 VSW2 ENABLE FB2 FB2S
ROC2 51.1k L2 1.0uH R10 2.15k C11 R8 1k R6 3.32k VOUT2 2.5V Cout2 470uF x2
R3 30.9k
PGND
RT SYNC
CC2
0.012uF
PGND
Fig. 14: IP1202PBF Dual Output Simplified Schematic 14 www.irf.com
IP1202PBF
VIN 12V Cin 22uF x6 R1 100k
HICCUP VIN OC1 VSW1 FB1 FB1S CC1
ROC1 51.1k L1 1.0uH R9 887 R7 1k Rshunt1 5mOhm
VOUT 1.5V Cout 470uF x4
C9 0.018uF R5 2.49k
R2 100k C8 0.1uF
PGOOD SS1
iP1202 IP1202PBF
SS2
VP-REF VREF
0.8V C10 100pF ROC2 51.1k L2 1.0uH R17 8.87k Rshunt2 5mOHM
OC2 VSW2 ENABLE FB2 FB2S PGND RT SYNC CC2
R3 30.9k PGND
C11 2.2nF R6 2.61k
Fig. 15: IP1202PBF Single Output Simplified Schematic
OC1
L1 1.0uH
Rdc1 (inductor dc resistance)
VIN 12V Cin 22uF x6 R1 100k
VOUT 1.5V Cout 470uF x4
VIN
VSW1
RL1 1.0k
CL1 1.0uF R9 887 R7 1k
HICCUP
FB1 FB1S
R2 100k
PGOOD
CC1
C9 0.018uF R5 2.49k
IP1202PBF iP1202 VP-REF
SS1 VREF
0.8V C10 100pF
C8 0.1uF
OC2 SS2 VSW2
L2 1.0uH RL2 1.0k
Rdc2 (inductor dc resistance)
CL2 1.0uF
ENABLE
FB2 FB2S CC2
R17 8.87k
R3 30.9k
PGND
RT SYNC
C11 2.2nF R6 2.61k
PGND
Fig. 16: IP1202PBF Single Output Lossless Inductor Current Sensing Simplified Schematic www.irf.com
15
IP1202PBF
IP1202PBF Design Procedure
Only a few external components are required to complete a dual output synchronous buck power supply using IP1202PBF. The following procedure will guide the designer through the design and selection process of these external components. A typical application for IP1202PBF will be: VIN = 12V, VOUT1 = 1.5V, IOUT1 = 15A, VOUT2 = 2.5V, IOUT2 = 10A, fsw = 300kHz, Vp-p1 = Vp-p2 = 50mV Setting the Output Voltage The output voltage of the IP1202PBF is set by the 0.8V reference Vref and external voltage dividers.
Vout1
ence source to VP-ref. In this case, to ensure proper start-up, power to VP-ref and IP1202PBF must be applied simultaneuosly. Setting the Overvoltage Trip Both outputs of the IP1202PBF will shut down if either one of the outputs experiences a voltage in the range of 115% of VOUT. The overvoltage sense pins FB1s and FB2s are connected to the output through voltage dividers, R13 and R14 (Fig. 17), and the trip setpoints are programmed according to equation (1). Separate overvoltage sense pins FB1s and FB2s are provided to protect the power supply output if for some reason the main feedback loop is lost (for instance, loss of feedback resistors). An optional 100pF capacitor (C26) is used for delay and filtering purposes. If this redundancy is not required and if Type II control loop compensation scheme is utilized, FB1s and FB2s pins can be connected to FB1 and FB2 pins respectively. In parallel configuration, FB2s should be connected to FB1s Setting the Soft-Start Capacitor The soft start capacitor Css is selected according to equation (2): tss = 40 x Css (2)
R9
FB1
R7
IP1202PBF iP1202
R13
FB1S
C26 (Optional)
R14
Fig. 17: Typical scheme for output voltage setting For Type II compensation, VOUT1 is set according to equation (1): VOUT1 = Vref x (1 + R9 /R7 ) (see Fig. 17) (1)
where, tss is the output voltage ramp time in milliseconds, and Css is the soft start capacitor in F. A 0.1F capacitor will provide an output voltage rampup time of about 4ms. Input Capacitor Selection The switching currents impose RMS current requirements on the input capacitors. The expression in equation (3) allows the selection of the input capacitors for duty cycles less than 0.5: 2 2 (3) I = I D (1 - D ) + I D (1 - D ) - 2 I I D D
RMS
Setting R7 to 1K, VOUT1 to 1.5V and Vref to 0.8V, will result in R9= 875 ohms (select 887 ohms). Final values can be selected according to the desired accuracy of the output. To set the output voltage for Type III compensation, refer to equation (25) in Type III compensation section. If the 0.8V reference is used to set the voltage for the second output VOUT2, VP-ref pin must be shorted to Vref pin and in a similar way, voltage divider resistors are selected for the second output VOUT2. The second output can also be set by applying an external refer16
(
1
1
1
2
2
2
12
1
2
)
where, I1 and I2 are the load currents for outputs 1 and 2 respectively and D1 and D2 are the duty cycles for channel 1 and channel 2 respectively. For output1 of the above example D= 0.13 and, For output2 of the above example D = 0.21 and, For the above example, using equation (3) the capacitor rms current yields 5.8A. www.irf.com
IP1202PBF
For better efficiency and low input ripple, select low ESR ceramic capacitors. The amount of the capacitors is determined based on the r.m.s. rating. In the above example, a total of 4 x 22F, 2A capacitors will be required to support the input r.m.s. current, including derating (see the parts list in the reference design section of this datasheet). The 180 out of phase operation of the IP1202PBF provides reduced voltage ripple at the input of the device. This reduction in ripple requires less input bypass capacitance. For single output configuration and a duty cycle greater than 0.5, select the input capacitors according to equation (4) :
I RMS = I LOAD
If the inductor current ripple Iripple is 30% of IOUT1, the 50mV peak to peak output voltage ripple requirement will be met if the total e.s.r. of the output capacitors is less than 11m. This will require 2 x 470F POSCAP capacitors (See the parts list in the reference design section of this datasheet). Additional ceramic capacitors can be added in parallel to further reduce the e.s.r. Care should be given to properly compensate the control loop for low output capacitor e.s.r. values. When selecting output capacitors, it is important to consider the overshoot performance of the power supply. If the amount of capacitance is not adequate, then, when unloading the output, the magnitude of the overshoot due to stored inductor energy, and depending on the speed of the response of the control loop, can exceed the overvoltage trip threshold of the IP1202PBF and can cause undesirable shutdown of the output. The magnitude of the overshoot should be kept below 1.125VOUT . To prevent the overshoot from tripping the output a delay can be added by installing capacitor C26 as shown in Fig.17. In paralleled single output configuration, due to 180 phase shift, the peak to peak output voltage ripple will be reduced because of doubling of the ripple frequency. Also, the resulting ripple current in the output capacitors will be smaller than the ripple current of each channel. There is some cancellation effect of these current, the magnitude of which depends on the duty cycle. b. Stability The value of the output capacitor e.s.r. zero frequency fesr plays a major role in determining stability. fesr is calculated by the expression in equation (8). fesr = 1 / (2 x Resr x CO) (8)
((2 - 2 D )(2 D - 1)
(4)
D is the duty cycle and is expressed as: D = VOUT / VIN. Output Capacitor CO Selection Selection of the output capacitors depends on two factors: a. Low effective ESR for ripple and load transient requirements To support the load transients and to stay within a specified voltage dip V due to the transients, e.s.r. selection should satisfy equation (5): Resr V / ILoadmax Where, ILoadmax is the maximum load current. If output voltage ripple is required to be maintained at specified levels then, the expression in equation (6) should be used to select the output capacitors. Resr Vp-p / Iripple (6) (5)
Where, Vp-p is the single phase peak to peak output voltage ripple. Iripple is the inductor current peak-to peak ripple. In addition, the voltage ripple caused by the output capacitor needs to be significantly smaller than the ripple caused by the ESR of the capacitor. Use equation (7) to satisfy this requirement.
Details on how to consider this parameter to design for stability will be outlined in the control loop compensation section of this datasheet. Inductor LO Selection Inductor selection is based on trade-offs between size and efficiency. Low inductor values result in smaller sizes, but can cause large ripple currents and lower efficiency. Low inductor values also benefit the transient performance. 17
Co >
10 2 f s Resr
(7)
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IP1202PBF
The inductor Lois selected according to equation (9): LO = Vout x (1 - D) / (fsw x Iripple) (9) Type II
Vout1
R9
IP1202PBF
iP1202
E/A1
For output 1 of the above example, and for Iripple of 30% of IOUT1, LO1 is calculated to be 1.0H. The core must be selected according to the peak of maximum output current. A similar calculation can be applied to find an inductor value for the second output. Control Loop Compensation The IP1202PBF feedback control is based on single loop voltage mode control principle if both outputs are configured in dual output independent mode. In this case, both outputs can have identical compensation. If IP1202PBF outputs are configured for parallel operation, then compensation of the outputs will differ slightly. The goal in the design of the compensator is to achieve the highest unity gain (0 db) crossover frequency with sufficient phase margin for the closed loop transfer function. The LC filter of the power supply introduces a double pole with 40db/dec slope and 1800 phase lag. The 180 phase contribution from the LC filter is the source of instabilty. The resonant frequency of the LC filter is expressed by equation (10):
FB1 R7 VREF C10
CC1 C9 (Optional)
R5
Magnitude(dB) H(s) dB
Fig. 18: Typical Type II compensation and its gain plot From Fig.18 the transfer function H(s) of the error amplifier is given by (11):
FZ
Frequency
f LC = 1 / (2 L0 x C 0 )
(10)
The error amplifiers of the IP1202PBF PWM controller are transconductance amplifiers, and their outputs are available for external compensation. Two type of compensators are studied in this section. The first one is called Type II and it is used to compensate systems the e.s.r. frequency fesr (equation 8) of which is in the midfrequency range and Type III that can be used for any type of output capacitors and have a wide range of fesr.
R7 1 + sR5 C9 (11) x R7 + R9 sC 9 R5 The term s represents the frequency dependence of the transfer function. H ( s) = g m x
The Type II controller introduces a gain and a zero expressed by equations (12) and (13):
H (s) = g m x R7 x R5 R7 + R9
(12)
where, gm is the transconductance of the error amplifier.
fz =
1 2 x R5 x C 9
(13)
Follow the steps below to determine the feedback loop compensation component values: 1. Select a zero db crossover frequency f0 in the range of 10% to 20% of the switching frequency fsw. www.irf.com
18
IP1202PBF
2. Calculate R5 using equation (14):
R5 =Vrampx 1.25
f xf R + R9 1 1 x 0 2esr x 7 x VIN R7 gm f LC
(14)
Where, VIN = Maximum Input voltage f0 = Error amplifier zero crossover frequency fesr= Output capacitor Co zero frequency fLC = Output frequency resonant filter gm= Error amplifier transconductance. Use 2mS for gm. Vramp = Oscillator ramp Voltage. Use 1.25V for Vramp 3. Place a zero at 75% of fLC to cancel one of the LC filter poles.
Type III Type III compensation scheme allows the use of any type of capacitors with esr frequency of any range. This scheme suggests a double pole double zero compensation and requires more components around the error amplifier to achieve the desired gain and phase margins. Fig. 19 represents the type III compensation network for IP1202PBF. The transfer function of the type III compensator is given by eqaution (18)
H (s) =
(1 + sR 23C 9 ) x (1 + sR9 C19 ) 1 x sR9 C 9 (1 + sR 23C18 ) x (1 + sR24 C19 )
(18)
C18
Vout1
f z = 0 . 75 x
1 2 Lo x C o
(15)
R23
C9
4. Calculate C9 using equations (13) and (15) Calculation of compensation components for output1, based on the example above yields: fLC = 5.0kHz fz = 3.8kHz f0 = 45kHz fesr = 14kHz, per equation (6) using Resr = 12m. R5 = 2.49K C9 = 18nF The same steps can be used to determine the values of the compensation components for output2. Sometimes, a pole fp2 is added at half the switching frequency to filter the switching noise. This is done by adding a capacitor Copt in Fig.18 from the output of the error amplifier (CC pin of IP1202PBF) to ground. This pole is given by equation (16):
C19 R24 R9 FB1 R7 VREF C10
E/A1
CC1
IP1202PBF iP1202
Magnitude(dB) H(s) dB
f p2
1 2 x R5 x Copt
(16)
FZ1
FZ2
FP2
FP3
Frequency
Copt is found from equation (17) by rearranging the terms in equation (16) and by setting fp2 = fsw / 2:
C opt =
1 2 x f p 2 x R5
Fig. 19: Typical Type III compensation and its gain plot
(17) 19
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IP1202PBF
The frequencies of the three poles and the two zeros of the type III compensation scheme are represented by the following equations: fp1= 0 (19) (20) 7. Place the second pole fp2 at or near fesr of the output capacitor Co and determine the value of R24 from R equation (20). Make sure R24 < 9
10
f p2
1 = 2 x R24 x C19
8. Use equation (25) to calculate R7. R7 = R9 x V ref (25) -V o ref More than one iteration may be required to calculate the values of the compensation components if crossover frequencies higher than the range specified in step 1 are required (for higher bandwidths and faster transient response performance). To ensure stability a phase margin greater than 45 should be achieved. Refer to AN-1043 for more detailed compensation techniques using Transconductance Amplifiers. Compensation in Current Share Mode
V
f p3
1 2 x R23 x C18
1 2 x R23 x C 9
(21)
f z1 =
(22)
f z2 =
1 2 x R9 x C19
(23)
The crossover frequency f0 for type III compensation is represented by equation (24):
f 0 = V .8 x VIN x R23 x C19 x 0
ramp
1
1 2 x L0 x C 0
(24)
The IP1202PBF can be configured in single output paralleled configuration. The feedback loop of the first output is closed around the output voltage, and the second amplifier, which is also a transconductance one, forces equal sharing of the inductor currents in both outputs. Voltage Loop Type II and Type III methods of voltage loop compensation discussed above, can be used to compensate the voltage loop of a single output IP1202PBF. In this case, the total amount of capacitance seen by both channels and the inductance of the voltage controlling channel should be considered for compensation. Current Loop Use the following procedure for current loop compensation: In Fig. 20, L1 and L2 are the inductors for outputs 1 and 2 respectively. Rsh1 and Rsh2 are the current sensing shunts for the same outputs.
Follow the steps below to determine the feedback loop compensation component values: 1. Select a zero db crossover frequency f0 in the range of 10% to 20% of the switching frequency fsw. 2. Select R23~ 10k 3. Place the first zero fz1 at 75% of the resonant frequency fLC of the output filter. Determine C9 from equation (22). 4. Place a third pole fP3 at or near the switching frequency fSW. Select C18 such that C18 <
C9 10
5. Calculate C19 from equation (24). 6. Place the second zero at 125% of the resonant frequency fLC of the output filter. Calculate R9 using equation (23). 20 www.irf.com
IP1202PBF
Vsw1 L1 Rsh1
IP1202PBF iP1202
E/A2
Vp-Ref
VOUT
FB2 CC2 C11 L2 R6 Vsw2
RLoad Rsh2
Fig. 20: Output 2 error amplifier compensation network for parallel configuration. Resistor R6 of the compensation network is calculated according to equation (26)
2 x L2 x f 02 1 (26) x g m x Rsh1 Vin It is recommended to set the channel 2 crossover frequency 30% higher than the voltage loop crossover frequency. R6 = Vramp x
The power stage of the current loop has a dominant pole at frequency expressed by equation (27):
fp =
Req 2 L2
(27)
where, Req represents the total resistance of the power stage that includes the Rdson of the FET switches, the DC resistance of the inductor and the shunt resistance, and is expressed by equation (28): (28) Req = Rdson + RL + Rsh use 10mohm for FET Rdson. To calculate for C11, place the zero frequency fz at 10 times the dominant pole frequency fp using equation (29):
f z = 10 x f p 1 C11 = 2 x R6 x f z Select C 11 6 .8 nf
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(29)
21
IP1202PBF
Typical Waveforms
Ch1
Ch3 Ch2 Ch4
Ch1: Output 1 switching node, 400kHz Ch2: Output 2 switching node, 400kHz Ch4: 800kHz external synchronization
Ch1: Ch2: Ch3: Ch4:
Output Output Output Output
1 2 1 2
voltage, 1V/div voltage, 1V/div load current, 10A/div load current, 10A/div
Fig. 21: IP1202PBF Outputs synchronized to 800kHz
Fig. 22: IP1202PBF hiccup response (Output 1 hiccups due to overload, whereas Output 2 continues uniterrupted)
Ch1: Output voltage, 100mV/div ac Ch3: Load current, 5A/div
Ch1: Output voltage, 100mV/div ac Ch3: Load current, 5A/div
Fig. 23: IP1202PBF Transient response load step 1A to 12A 22
Fig. 24: IP1202PBF Transient response load step 12A to 0A www.irf.com
IP1202PBF
Ch1
Ch3 Ch2 Ch4
Ch1: Ch2: Ch3: Ch4:
Output Output Output Output
1 2 1 2
voltage, 1V/div voltage, 1V/div load current, 10A/div load current, 10A/div
Vin=3.3V Ch1: Output Ch2: Output Ch3: Output Ch4: Output
1 switch node voltage 10V/div 2 switch node voltage 10V/div 1 inductor current, 10A/div 2 inductor current , 10A/div
Fig. 25: IP1202PBF latched overcurrent response (output1 shutsdown due to overload, whereas output2 continues uninterrupted)
Fig. 26: IP1202PBF inductor current sharing
Ch1: Output1 voltage, 1V/div Ch2: Output2 voltage, 1V/div
Vin=12V Ch1: Output 1 switch node voltage 10V/div Ch2: Output 2 switch node voltage 10V/div Ch3: Output voltage ripple, 50mV/div
Fig. 27: IP1202PBF overvoltage trip. (Overvoltage on output2 causes both outputs to shutdown) www.irf.com
Fig. 28: IP1202PBF Output voltage ripple in parallel configuration 23
IP1202PBF
Ch1: Output 1, 0.5V/div Ch2: Output 2, 0.5V/div
Ch1: Output 1, 0.5V/div Ch2: Output 2, 0.5V/div
Fig. 29: IP1202PBF output sequencing with separate soft-start capacitors
Fig. 30: IP1202PBF output sequencing with separate soft-start capacitor and delayed turn-on
24
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IP1202PBF
Layout Guidelines For stable and noise free operation of the whole power system, it is recommended that the designer uses the following guidelines: 1. Follow the layout scheme presented in Fig. 32. Make sure that the output inductors L1 and L2 are placed as close to IP1202PBF as possible to prevent noise propagation that can be caused by switching of power at the switching node Vsw, to sensitive circuits. 2. Provide a mid-layer solid ground plane with connections to the top layer through vias. The PGND pads of IP1202PBF also need to be connected to the same ground plane through vias. 3. To increase power supply noise immunity, place input and output capacitors close to one another, as shown in the layout diagram. This will provide short high current paths that are essential at the ground terminals. 4. Although there is a certain degree of VIN bypassing inside the IP1202PBF, the external input decoupling capacitors should be as close to the device as possible. 5. The Feedback tracks from the outputs VOUT1 and VOUT2 to FB1 and FB2 respectively, should be routed as far away from noise generating traces as possible. 6. The compensation components and the Vref bypass capacitor should be placed as close as possible to their corresponding IP1202PBF pins. 7. For single output configuration, the parasitic paths leading to the common output connector from each parallel branch should be symmetrically routed to ensure equal current sharing. 8. Refer to IR application note AN-1029 to determine what size vias and copper weight and thickness to use when designing the PCB. 9. Place the overcurrent threshold setting resistors ROCSET1 and ROCSET2 close to the IP1202PBF block at the corresponding connection nodes.
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Fig. 31: IP1202PBF suggested layout
25
IP1202PBF
PGNDS
1
2
1
2
PGND
26
VIN
VIN VSW1 OC1
JP1-1
JP3-1
TP3
VSW1S
VIN
TP28 VIN
SHUNT
SHUNT
TP1
OC1 ROC1
TP8 VSW1 L1 1uH FB1 R23 NI C18*** NI NI C9 0.018uF NI R24*** C19 *** R9** 887 1% C12 470uF 5mOHM (short for independent output configuration) C13 470uF C24 NI 51.1K 1% VSW1
TP15 VOUT1
VIN VIN=5.5V-13.2V
R15
VOUT1
(1.5V)
TP11 VOUT C14 0.1uF TP20 VOUT TP14 PGND TP16 PGND
TP2
25V
FB1
C1 22uF
25V *** 6.3V 6.3V
C2 22uF
25V
C3 22uF
25V
C4 22uF
25V
C22 22uF
25V
C23 22uF
PGND
TP4
TP29 PGND
PGND VIN 100K
CC1 HICCUP
CON4 R1 HICCUP CC1
1
2
ENABLE
VINS
**
3
4
R5 R7 2.49K 1K 1%
TP22 PGN
5 FB1S
6
VSW1S
JP1 HICCUP FB1S 887 1% C26 100pF
PGOOD VP-REF
R13
7
8
VSW2S
9
10
VOUT1
11
12
VIN PGOOD VP-REF 100K
R2
R14 1K 1%
VOUT2
R27 0
13
14
15
16
R4
0 SS1
SS1 VREF
R16 0
VREF C10 100pF ROC2 51.1K 1% TP10 VSW2 L2 1uH
VSW2S
0.8V
Type III Compensation
INPUT/OUTPUT C8 0.1uF
OC2
iP1202 PbF
OC2
SS2
SS2 VSW2
Compensation Configuration
VSW2
TP17 VOUT2 R19 R17 8.87k
Designator Installed Installed Installed Installed FB2
Type II Configuration
Type III Configuration

5mOHM (short for independent output configuration)
VOUT2
(2.5V)
TP1 VOU
R23, R24, R25, R26
Removed
C18, C19
Removed
C7 0.1uF
C20, C21
Removed
R10
C9, C11
Installed
FB2
2.15k 1%
C15 470uF
6.3V *** R25
NI R26 NI R8 1k 1%
6.3V *** *** C21
NI
C16 470uF
C25 NI
C17 0.1uF TP1 PGN
Fig. 32: Reference Design Schematic
Removed
R5, R6
Installed
ENABLE
ENABLE
C20*** NI
JP3 ENABLE
CC2
C11 0.012uF R6 3.32K
TP18 PGND
CC2
Output Configuration
R3 RT
RT FB2S
Designator 5mOHM Installed Installed
TP6 SYNC
SYNC
Independent mode(dual output)
2 phase mode(single output)
FB1S R22 0 FB2S C27 100pF R11 2.15K 1% **For independent mode, output voltages are set by using the following equations: R12 1K 1%
R15, R19
30.9K
Short
R16 Removed Removed Removed Removed Installed
SYNC
Removed
R17
Removed
R8
Installed
R10
Installed
For VOUT1: R9 = R7[(VOUT1/VREF) - 1].
For VOUT2: R10 = R8[(VOUT2/VREF) - 1]. Set R7 (or R8) to 1K, VREF to 0.8V, and VOUT to desired output, then solve for R9 (or R10 respectively). For parallel (single output) mode, check table on the left. NI: *** Not Installed
R4
Installed
R11 R12
Installed
R22 R27
Removed
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IP1202PBF
IRDCiP1202-A (Single, paralleled output configuration(for 1.5V output)
QTY 6 4 1 4 3 1 2 2 2 2 2 1 2 1 15 2 1 1 1 1 REF DESIGNATOR C1, C2, C3, C4, C22, C23 C7, C8, C14, C17 C11 C12, C13, C15, C16 C10, C26, C27 C9 L1, L2 R13, R9 R7, R14 ROC1,ROC2 R15, R19 R27 R16, R22 R17 C18, C19, C20, C21, C24, C25, R10, R11, R12, R4, R8, R23, R24, R25, R26 R1, R2 R5 R6 R3 U1 DESCRIPTION Capacitor, ceramic, 22F, 25V, X5R, 20% Capacitor, ceramic, 0.1F, 50V, X7R, 10% Capacitor, ceramic, 0.012uF, 25V, X7R, 10% Capacitor, poscap, 470F, 6.3V, electrolytic 20% Capacitor, ceramic, 100pF, 50V, NPO, 5% Capacitor, ceramic, 0.018uF, 25V, X7R, 10% Inductor, 1H, 19A, 20% Resistor, thick film, 887, 1/10W , 1% Resistor, thick film, 1.0k, 1/10W , 1% Resistor, thick film, 51.1k, 1/10W , 1% Resistor, alloy metal, 5m, 1W , 1% Resistor, manganin-foil, 0, 2W Resistor, thick film, 0, 1/16W Resistor, thick film, 8.87k, 1/10W , 1% Not installed Resistor, thick film, 1/10W , 1% Resistor, thick film, 1/10W , 1% Resistor, thick film, 1/10W , 1% Resistor, thick film, 1/10W , 1% BGA Power Block 100k, 2.49k, 3.32k, 30.9k, SIZE 1812 0603 0603 7343 0603 0603 TDK TDK Phycomp Sanyo Phycomp Phycomp MFR PART NUMBER C4532X5R1E226M C1608X7R1H104K 06032R123K8B20 6TPB470M 0603CG101J9B20 06032R183K8B20 ETQP1H1R0BFA RK73H1J8870F RK73H1J1001F RK73H1J5112F ERJM1W SF5M0U SMT-R000 MCR03EZHJ000 RK73H1J8871F RK73H1J1003F RK73H1J2491F RK73H1JLTD3321F RK73H1J3092F iP1202
13.0mm X 12.9mm Panasonic 0603 0603 0603 2512 2716 0603 0603 0603 0603 0603 0603 KOA KOA KOA Panasonic Isotek Corp ROHM KOA KOA KOA KOA KOA
9.25mm X 15.5mm IR
IRDCiP1202-A (Dual, Independent output configurations(Channel1 1.5V output, Channel2 2.5V output)
QTY 6 4 1 4 3 1 2 2 2 4 2 2 1 14 2 1 1 1 1 REF DESIGNATOR C1, C2, C3, C4, C22, C23 C7, C8, C14, C17 C11 C12, C13, C15, C16 C10, C26, C27 C9 L1, L2 R13, R9 R10, R11 R7, R8, R12, R14 ROC1,ROC2 R15, R19 R4 C18, C19, C20, C21, C24, C25, R16, R17, R22, R23, R24, R25, R26, R27 R1, R2 R5 R6 R3 U1 DESCRIPTION Capacitor, ceramic, 22F, 25V, X5R, 20% Capacitor, ceramic, 0.1F, 50V, X7R, 10% Capacitor, ceramic, 0.012uF, 25V, X7R, 10% Capacitor, poscap, 470F, 6.3V, electrolytic 20% Capacitor, ceramic, 100pF, 50V, NPO, 5% Capacitor, ceramic, 0.018uF, 25V, X7R, 10% Inductor, 1H, 19A, 20% Resistor, thick film, 887, 1/10W, 1% Resistor, thick film, 2.15k, 1/10W, 1% Resistor, thick film, 1.0k, 1/10W, 1% Resistor, thick film, 51.1k, 1/10W, 1% Resistor, manganin-foil, 0, 2W Resistor, thick film, 0, 1/10W, 5% Not installed Resistor, thick film, 100k, 1/10W, 1% Resistor, thick film, 2.49k, 1/10W, 1% Resistor, thick film, 3.32k, 1/10W, 1% Resistor, thick film, 30.9k, 1/10W, 1% BGA Power Block SIZE 1812 0603 0603 7343 0603 0603 13.0mm X 12.9mm 0603 0603 0603 0603 2716 0603 0603 0603 0603 0603 9.25mm X 15.5mm MFR TDK TDK Phycomp Sanyo Phycomp Phycomp Panasonic KOA KOA KOA KOA Isotek Corp ROHM KOA KOA KOA KOA IR PART NUMBER C4532X5R1E226M C1608X7R1H104K 06032R123K8B20 6TPB470M 0603CG101J9B20 06032R183K8B20 ETQP1H1R0BFA RK73H1J8870F RK73H1J2151F RK73H1J1001F RK73H1J5112F SMT-R000 MCR03EZHJ000 RK73H1J1003F RK73H1J2491F RK73H1JLTD3321F RK73H1J3092F iP1202
www.irf.com
Table 2. Reference Design Bill of Materials
27
IP1202PBF
0.15 [.006] C 2X 6 15.50 [.610] B A 5 C 0.45 [.0177] 0.35 [.0138] 0.12 [.005] C BALL A1 CORNER ID 9.25 [.364] NOT ES : 1. 2. 3. 4. 5 6 7 0.15 [.006] C 2X 6 DIMENS IONING & T OLERANCING PER AS ME Y14.5M-1994. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ]. CONT ROLLING DIMENS ION: MILLIMET ER S OLDER BALL POS IT ION DES IGNAT ION PER JES D 95-1, S PP-010. PRIMARY DAT UM C (S EAT ING PLANE) IS DEFINED BY T HE S PHERICAL CROWNS OF T HE S OLDER BALLS . BILAT ERAL T OLERANCE ZONE IS APPLIED T O EACH S IDE OF T HE PACKAGE BODY. S OLDER BALL DIAMET ER IS MEAS URED AT T HE MAXIMUM S OLDER BALL DIAMET ER, IN A PLANE PARALLEL T O DATUM C.
8. NOT T O S CALE
T OP VIEW
161X O
0.55 [.0216] 0.45 [.0178]
7
0.15 [.006] 0.08 [.003]
CAB C
0.40 [.016] 2X
0.80 [.032] 27X
(2X 0.625 [.025])
2.33 [.0917] 2.11 [.0831] 2.78 [.1094] 2.46 [.0968]
BOT T OM VIEW
S IDE VIEW
Fig.33: Mechanical Drawing Refer to the following application notes for detailed guidelines and suggestions when implementing iPOWIR Technology products: AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifiers iPOWIR Technology BGA Packages This paper discusses the assembly considerations that need to be taken when mounting iPOWIR BGAs on printed circuit boards. This includes soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1043: Stabilize the Buck Converter with Transconductance Amplifier. AN-1047: Graphical solution to two branch heatsinking Safe Operating Area This paper is a suppliment to AN-1030 and explains how to use the double side Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1053: Power Sequencing Techniques using iP1201 and IP1202PBF. 28 www.irf.com
IP1202PBF
BALL A1 IDENTIFIER INTERNATONAL RECTIFIER LOGO ASSEMBLY CODE DATE CODE (YYWW) YY=YEAR WW=WEEK PART NUMBER FACTORY CODE
Fig.34: Part Marking
0305 XXXX iP1202 IP1202PBF
0520 XXXX IP1202PBF
0520 XXXX IP1202PBF
24.00 (.945)
20.00 (.787)
FEED DIRECT ION NOT ES : 1. OUT LINE CONFORMS TO EIA-481 & EIA-541. IP1202PBF, BGA
Fig.35: Tape & Reel Information
Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.8/06 www.irf.com 29

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